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version 4.1 september 2003 1/45 TDA9115 low-cost i 2 c controlled deflection processor for multisync monitor features general n i 2 c-bus-controlled deflection processor dedicated for low-end crt monitors n single supply voltage 12v n very low jitter n dc/dc converter controller n advanced ew drive n automatic multistandard synchronization n dynamic correction waveform output n x-ray protection and soft-start & stop on horizontal and dc/dc drive outputs horizontal section n 150 khz maximum frequency n corrections of geometric asymmetry: pin cushion asymmetry, parallelogram n tracking of asymmetry corrections with vertical size and position n horizontal moir cancellation output vertical section n 200 hz maximum frequency n vertical ramp for dc-coupled output stage with adjustments of: c-correction, s-correction for super-flat crt, vertical size, vertical position n vertical moir cancellation through vertical ramp waveform n compensation of vertical breathing with eht variation ew section n symmetrical geometry corrections: pin cushion, keystone n horizontal size adjustment n tracking of ew waveform with vertical size and position and adaptation to frequency n compensation of horizontal breathing through ew waveform dynamic correction section n vertical dynamic correction waveform output for dynamic corrections like focus, brightness uniformity, ... n fixed on screen by means of tracking system dc/dc controller section n step-up and step-down conversion modes n external sawtooth configuration n synchronization on hor. frequency with phase selection n selectable polarity of drive signal description the TDA9115 is a monolithic integrated circuit as- sembled in a 32-pin shrink dual-in-line plastic package. this ic controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. the device only requires very few external compo- nents. combined with other st components dedicated for crt monitors (microcontroller, video preampli- fier, video amplifier, osd controller) the TDA9115 allows fully i 2 c bus-controlled computer display monitors to be built with a reduced number of ex- ternal components. ordering information ordering code package TDA9115 shrink 32 (plastic) 1
table of contents 2 2/45 1 -pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 -block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 -pin function reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 -quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 -absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 -electrical parameters and operating conditions . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 supply and reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 synchronization inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.5 vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 6.6 ew drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.7 dynamic correction outputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.8 dc/dc controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.9 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 -typical output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 -i 2 c bus control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 -operating description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1 supply and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.1 power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.2 i 2 c bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 sync. processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.1 synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.2 automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3 horizontal section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3.2 pll1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3.3 voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3.4 pll2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3.5 dynamic pll2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3.6 output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3.7 soft-start and soft-stop on h-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3.8 horizontal moir cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.4 vertical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 9.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.4.2 vertical moir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.5 ew drive section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.6 dynamic correction output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.6.1 vertical dynamic correction output vdycor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7 dc/dc controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.8 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.8.1 safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 9.8.2 soft start and soft stop functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.8.3 x-ray protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.8.4 composite output hlckvbk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 -internal schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 -package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 -glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TDA9115 3/45 1 - pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 h/hvsyn vsyn hlckvbk hpll2c co hgnd ro hpll1f hposf hmoir hfly refout bcomp bregin bisense hoscf hehtin vehtin voscf vagccap vgnd vcap vout ewout xray hout gnd bout vcc scl sda vdycor
TDA9115 4/45 2 - block diagram TDA9115 horizontal vco phase/frequency comparator horizontal position lock detection pll1 v-sync detection input selection polarity handling vertical oscillator with agc s-correction c-correction pll2 phase comparator phase shifter h duty controller pin cushion asymm. parallelogram h-drive buffer h-moir controller h-moir amplitude v-sync extraction & detection geometry tracking v-dynamic correction (focus, bright.) vdycor amplitude h-sync detection polarity handling v-blank h-lock 3 hlckvbk safety processor 25 xray 11 hmoir 32 vdycor 19 voscf 21 vgnd 2 vsyn 27 gnd 26 hout 5 hpll2c 12 hfly 4 hoscf 6 c0 8 r0 9 hpll1f 10 hposf 7 hgnd h/hvsyn 1 i 2 c bus interface 31 sda scl 30 supply supervision reference generation 13 refout 29 vcc i 2 c bus registers b+ dc/dc converter controller 28 bout 16 bisense 15 bregin 14 bcomp vagccap 20 22 vcap v-ramp control tracking eht vertical size vertical position vertical moir 18 vehtin 23 vout 17 hehtin ew generator pin cushion keystone 24 ewout internal ref. : functions controlled via i 2 c bus h size
TDA9115 5/45 3 - pin function reference pin name function 1 h/hvsyn ttl compatible h orizontal / h orizontal and v ertical syn c. input 2 vsyn ttl compatible v ertical syn c. input 3 hlckvbk h orizontal pll1 l o ck detection and v ertical early b lan k ing composite output 4 hoscf high h orizontal osc illator sawtooth threshold level f ilter input 5 hpll2c h orizontal pll2 loop c apacitive filter input 6 co horizontal o scillator c apacitor input 7 hgnd h orizontal section g rou nd 8 ro horizontal o scillator r esistor input 9 hpll1f h orizontal pll1 loop f ilter input 10 hposf h orizontal pos ition f ilter and soft-start time constant capacitor input 11 hmoir h orizontal moir cancellation output 12 hfly h orizontal fly back input 13 refout ref erence voltage out put 14 bcomp b + dc/dc error amplifier ( comp arator) output 15 bregin reg ulation feedback in put of the b + dc/dc converter controller 16 bisense b + dc/dc converter current ( i ) sense input 17 hehtin in put for compensation of h orizontal amplitude versus eht variation 18 vehtin in put for compensation of v ertical amplitude versus eht variation 19 voscf v ertical osc illator sawtooth low threshold f ilter (capacitor to be connected to vgnd) 20 vagccap input for storage cap acitor for a utomatic g ain c ontrol loop in v ertical oscillator 21 vgnd v ertical section g rou nd 22 vcap v ertical sawtooth generator cap acitor 23 vout v ertical deflection drive out put for a dc-coupled output stage 24 ewout e / w out put 25 xray x - ray protection input 26 hout h orizontal drive out put 27 gnd main g rou nd 28 bout b + dc/dc converter controller out put 29 vcc supply voltage 30 scl i 2 c bus s erial cl ock input 31 sda i 2 c bus s erial da ta input/output 32 vdycor v ertical dy namic cor rection output
TDA9115 6/45 4 - quick reference data characteristic value unit general package sdip 32 supply voltage 12 v supply current 55 ma application category low-end means of control/maximum clock frequency i 2 c bus/400 khz ew drive yes dc/dc convertor controller yes horizontal section frequency range 15 to 150 khz autosync frequency ratio (can be enlarged in application) 4.28 positive/negative polarity of horizontal sync signal/automatic adaptation yes/yes/yes duty cycle of the drive signal 48 % position adjustment range with respect to h period 11 % soft start/soft stop feature yes/yes hardware/software pll lock indication yes/no parallelogram yes pin cushion asymmetry correction (also called side pin balance) yes top/bottom/common corner asymmetry correction no/no/no tracking of asymmetry corrections with vertical size & position yes horizontal moir cancellation (ext.) for combined/separated architecture yes/yes vertical section frequency range 35 to 200 hz autosync frequency range (150nf at vcap and 470nf at vagccap) 50 to 180 hz positive/negative polarity of vertical sync signal/automatic adaptation yes/yes/yes s-correction/c-correction/super-flat tube characteristic yes/yes/yes vertical size/vertical position adjustment yes/yes vertical moir cancellation (internal) yes vertical breathing compensation yes ew section pin cushion correction yes keystone correction yes top/bottom/common corner correction no/no/no horizontal size adjustment yes tracking of ew waveform with frequency/vertical size & position yes/yes breathing compensation on ew waveform yes dynamic correction section (dyn. focus, dyn. brightness,...) vertical dynamic correction output vdycor yes horizontal dynamic correction output no composite hv dynamic correction output no tracking of horizontal waveform with horizontal size/eht no/no tracking of vertical waveform with v. size & position yes dc/dc controller section step-up/step-down conversion mode yes/yes internal/external sawtooth configuration no/yes bus-controlled output voltage no soft start/soft stop feature yes/yes positive(n-mos)/negative(p-mos) polarity of bout signal yes/yes
TDA9115 7/45 5 - absolute maximum ratings all voltages are given with respect to ground. currents flowing from the device (sourced) are signed negative. currents flowing to the device are signed positive. symbol parameter value unit min max v cc supply voltage (pin vcc) -0.4 13.5 v v (pin) pins hehtin, vehtin, xray, hout, bout pins h/hvsyn, vsyn, scl, sda pins hlckvbk, co, ro, hpll1f, hposf, hmoir, bregin, bi- sense, vagccap, vcap, vdycor, hoscf, voscf pin hpll2c pin hfly -0.4 -0.4 -0.4 -0.4 -0.4 v cc 5.5 v refo v refo /2 v refo v v v v v v esd esd susceptibility (human body model: discharge of 100pf through 1.5k w ) -2000 2000 v t stg storage temperature -40 150 c t j junction temperature 150 c
TDA9115 8/45 6 - electrical parameters and operating conditions medium (middle) value of an i 2 c bus control or adjustment register composed of bits d0, d1,...,dn is the one having dn at "1" and all other bits at "0". minimum value is the one with all bits at 0, maximum value is the one with all at "1". currents flowing from the device (sourced) are signed negative. currents flowing to the device are signed positive. t h is period of horizontal deflection. 6.1 thermal data 6.2 supply and reference voltages t amb = 25c 6.3 synchronization inputs vcc = 12v, t amb = 25c symbol parameter value unit min. typ. max. t amb operating ambient temperature 0 70 c r th(j-a) junction-ambience thermal resistance 65 c/w symbol parameter test conditions value units min. typ. max. v cc supply voltage at vcc pin 10.8 12 13.2 v i cc supply current to vcc pin v cc = 12v 55 ma v refo reference output voltage at refout pin v cc = 12v, i refo = -2ma 7.4 8 8.6 v i refo current sourced by refout output -5 0 ma symbol parameter test conditions value units min. typ. max. v loh/hvsyn low level voltage on h/hvsyn 0 0.8 v v hih/hvsyn high level voltage on h/hvsyn 2.2 5 v v lovsyn low level voltage on vsyn 0 0.8 v v hivsyn high level voltage on vsyn 2.2 5 v r pdsyn internal pull-down on h/hvsyn, vsyn 100 175 250 k w t pulsehsyn h sync. pulse duration on h/hvsyn pin 0.5 m s t pulsehsyn /t h proportion of h sync pulse to h period pin h/hvsyn 0.2 t pulsevsyn v sync. pulse duration pins h/hvsyn, vsyn 0.5 750 m s t pulsevsyn /t v proportion of v sync pulse to v period pins h/hvsyn, vsyn 0.15 t extrv /t h proportion of sync pulse length to h peri- od for extraction as v sync pulse pin h/hvsyn, cap. on pin co = 820pf 0.21 0.3 t hpoldet polarity detection time (after change) pin h/hvsyn 0.75 ms
TDA9115 9/45 6.4 horizontal section vcc = 12v, t amb = 25c symbol parameter test conditions value units min. typ. max. pll1 i ro current load on ro pin 1.5 ma c co capacitance on co pin 390 pf f ho frequency of hor. oscillator 150 khz f ho(0) free-running frequency of hor. oscill. (1) r ro =5.23k w , c co =820pf 27 28.5 29.9 khz f hocapt hor. pll1 capture frequency (4) f ho(0) = 28.5khz 29 122 khz temperature drift of free-running freq. (3) -150 ppm/c d f ho /d v ho average horizontal oscillator sensitivity f ho(0) = 28.5khz 19.6 khz/v v ho h. oscill. control voltage on pin hpll1f v refo =8v 1.4 6.0 v v hothrfr threshold on h. oscill. control voltage on hpll1f pin for tracking of ew with freq. v refo =8v 5.0 v v hposf control voltage on hposf pin hpos (sad01): 11111111b 10000000b 00000000b 2.60 3.30 3.85 2.8 3.4 4.0 3.05 3.55 4.15 v v v v hothrlo bottom of hor. oscillator sawtooth (6) 1.6 v v hothrhi top of hor. oscillator sawtooth (6) 6.4 v pll2 r in(hfly) input impedance on hfly input (2) v (hfly) >v thrhfly 300 500 700 w i inhfly current into hfly input at top of h flyback pulse 5 ma v thrhfly voltage threshold on hfly input 0.6 0.7 v v s(0) h flyback lock middle point (6) no pll2 phase modula- tion 4.0 v v bothpll2c low clamping voltage on hpll2c pin (5) 1.6 v v tophpll2c high clamping voltage on hpll2c pin (5) 3.75 4.0 4.25 v t ph (min)/t h min. advance of h-drive off before middle of h flyback (7) null asym. correction 0 % t ph (max)/t h max. advance of h-drive off before middle of h flyback (8) null asym. correction 44 % h-drive output on pin hout i hout current into hout output output driven low 30 ma t hoff /t h duty cycle of h-drive signal soft-start/soft-stop value 48 85 % % picture geometry corrections through pll1 & pll2 t hph /t h h-flyback (center) static phase vs. sync signal (via pll1), see figure 7 hpos (sad01): 11111111b 00000000b +11 -11 % % f ho 0 () d f ho 0 () t d ---------------------------- -
TDA9115 10/45 note 1: frequency at no sync signal condition. for correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency. the application must consider the spread of values of real electrical components in r ro and c co positions so as to always meet this condition. the formula to calculate the free-running frequency is f ho(0) =0.12125/(r ro c co ) note 2: base of npn transistor with emitter to ground is internally connected on pin hfly through a series resistance of about 500 w and a resistance to ground of about 20k w. note 3: evaluated and figured out during the device qualification phase. informative. not tested on every single unit. note 4: this capture range can be enlarged by external circuitry. note 5: the voltage on hpll2c pin corresponds to immediate phase of leading edge of h-drive signal on hout pin with respect to internal horizontal oscillator sawtooth. it must be between the two clamping levels given. voltage equal to one of the clamping values indicates a marginal operation of pll2 or non-locked state. note 6: internal threshold. see figure 7. note 7: the t ph (min)/t h parameter is fixed by the application. for correct operation of asymmetry corrections through dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required in the direction leading to bending of corners to the left. marginal situation is indicated by reach of v tophpll2c high clamping level by waveform on pin hpll2c. also refer to note 5 and figure 7. note 8: the t ph (max)/t h parameter is fixed by the application. for correct operation of asymmetry corrections through dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in the direction leading to bending of corners to the right. marginal situation is indicated by reach of v bothpll2c low clamping level by waveform on pin hpll2c. also refer to note 5 and figure 7 . note 9: all other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions. t pcac /t h contribution of pin cushion asymmetry correction to phase of h-drive vs. static phase (via pll2), measured in corners (9 pcac (sad11h) full span vpos at medium vsize at minimum vsize at medium vsize at maximum 1.0 1.8 2.8 % % % t paralc /t h contribution of parallelogram correction to phase of h-drive vs. static phase (via pll2), measured in corners (9) paral (sad12h) full span vpos at medium vsize at minimum vsize at medium vsize at maximum vpos at max. or min. vsize at minimum 1.75 2.2 2.8 1.75 % % % % symbol parameter test conditions value units min. typ. max.
TDA9115 11/45 6.5 vertical section v cc = 12v, t amb = 25c note 10: value of acceptable cumulated parasitic load resistance due to humidity, agc storage capacitor leakage, etc., for less than 1% of v amp change. symbol parameter test conditions value units min. typ. max. agc-controlled vertical oscillator sawtooth; v refo = 8v r l(vagccap) ext. load resistance on vagccap pin (10) d v amp /v amp (r= ) 1% 65 m w v vob sawtooth bottom voltage on vcap pin (11) no load on voscf pin (11) 1.8 1.9 2.0 v v vot sawtooth top voltage on vcap pin agc loop stabilized v sync present no v sync 5 4.9 v v t vodis sawtooth discharge time c vcap =150nf 80 m s f vo(0) free-running frequency c vcap =150nf 100 hz f vocapt agc loop capture frequency c vcap =150nf 50 185 hz sawtooth non-linearity (12) agc loop stabilized, (12) 0.5 % s-correction range agc loop stabilized, (13) t vr =1/4 t vr (15) t vr =3/4 t vr -5 +5 % % c-correction range agc loop stabilized, (14) t vr =1/2 t vr (15) ccor (sad0a): x0000000b x1000000b x1111111b -3 0 +3 % % % frequency drift of sawtooth amplitude (17)(18) agc loop stabilized f vocapt (min) f vo f vocapt (max) 200 ppm/hz vertical output drive signal (on pin vout ); v refo = 8v v mid(vout) middle point on vout sawtooth vpos (sad08): x0000000b x1000000b x1111111b 3.65 3.2 3.5 3.8 3.3 v v v v amp amplitude of vout sawtooth (peak-to-peak voltage) vsize (sad07): x0000000b x1000000b x1111111b 3.5 2.25 3.0 3.75 2.5 v v v v offvout level on vout pin at v-drive "off" i 2 cbit vouten at 0 3.8 v i vout current delivered by vout out- put -5 5 ma v veht control input voltage range on vehtin pin 1 v refo v breathing compensation v veht > v refo v veht (min) v veht v refo 0 2.5 %/v %/v v vodev d v voamp 16 () -------------------------------- - v vos cor C d v voamp -------------------------------- v voc cor C d v voamp -------------------------------- v voamp d v voamp f vo d ---------------------------------------- - v amp d v amp v veht d ----------------------------------------- -
TDA9115 12/45 note 11: the threshold for v vob is generated internally and routed to voscf pin. any dc current on this pin will influence the value of v vob . note 12: maximum of deviation from an ideally linear sawtooth ramp at null scor (sad09 at x0000000b) and null ccor (sad0a at x1000000b). the same rate applies to v-drive signal on vout pin. note 13: maximum scor (sad09 at x1111111b), null ccor (sad0a at x1000000b). note 14: null scor (sad09 at x0000000b). note 15: "t vr " is time from the beginning of vertical ramp of v-drive signal on vout pin. "t vr " is duration of this ramp, see chapter typical output waveforms and figure 19. note 16: v voamp = v vot -v vob note 17: the same rate applies to v-drive signal on vout pin. note 18: informative, not tested on each unit. 6.6 ew drive section v cc = 12v, t amb = 25c symbol parameter test conditions value units min. typ. max. v ew output voltage on ewout pin 1.8 6.5 v i ewout current sourced by ewout out- put -1.5 0 ma v heht control voltage range on heh- tin pin 1v refo v v ew-dc dc component of the ew-drive signal on ewout pin (19)(20)(21)(28) t vr =1/2 t vr (15) hsize (sad10h): 00000000b 10000000b 11111111b 2 3.25 4.5 v v v breathing compensation on v ew-dc (19)((20) t vr =1/2 t vr (15) v heht > v refo v heht (min) v heht v refo 0 -0.125 v/v v/v temperature drift of dc compo- nent of the ew-drive signal on ewout pin (18)(19)(21)(28) t vr =1/2t vr (15) 100 ppm/c v ew-pcc pin cushion correction compo- nent of the ew-drive signal on ewout pin (19)(21)(22)(23)(24)(28) vsize at maximum pcc (sad0c): x0000000b x1000000b x1111111b tracking with vsize : pcc at x1000000b vsize (sad07): x0000000b x1000000b 0 0.7 1.5 0.25 0.5 v v v v v tracking of pcc component of the ew-drive signal with vertical position adjustment (19)(22)(25)(27)(28) pcc at x1111111b vpos (sad08): x0000000b x1111111b 0.52 1.92 v ew dc C d v heht d ----------------------------- v ew dc C d v ew dc C t d ------------------------------------- v ew pcc C t vr 0 = [] v ew pcc C t vr t vr = [] -- --------------------------------------------------------
TDA9115 13/45 note 19: keyst at medium (neutral) value. note 20: pcc at minimum value. note 21: vpos at medium (neutral) value. note 22: hsize at minimum value. note 23: defined as difference of (voltage at t vr =0) minus (voltage at t vr =1/2 t vr ). note 24: defined as difference of (voltage at t vr =t vr ) minus (voltage at t vr =1/2 t vr ). note 25: vsize at maximum value. note 26: difference: (voltage at t vr =0) minus (voltage at t vr =t vr ). note 27: ratio "a/b"of parabola component voltage at t vr =0 versus parabola component voltage at t vr =t vr . see figure 2. note 28: v heht > v refo , v veht > v refo note 29: v ew-ac is the sum of all components other than v ew-dc (contribution of pcc and keystone correction). note 30: more precisely tracking with voltage on hpll1f pin which itself depends on frequency at a rate given by external components on pll1 pins. v ew [fmax] is the value at condition v ho >v hothrfr . v ew-key keystone correction component of the ew-drive signal on ewout pin (20)(21)(22)(25)(26)(28) keyst (sad0d): x0000000b x1111111b 0.4 -0.4 v v tracking of ew-drive signal with horizontal frequency (30) v ho > v hothrfr v ho (min) v ho v hothrfr 0 20 %/v %/v breathing compensation on v ew-ac (29) (23)(24) v heht > v refo v heht (min) v heht v refo 0 1.75 %/v %/v symbol parameter test conditions value units min. typ. max. v ew d v ew f max [] v ho d --------------------------------------------------------- v ew ac C d v ew ac C v heht d ---------------------------------------------------- -
TDA9115 14/45 6.7 dynamic correction outputs section v cc = 12v, t amb = 25c note 31: ratio "a/b"of vertical parabola component voltage at t vr =0 versus vertical parabola component voltage at t vr =t vr . symbol parameter test conditions value units min. typ. max. vertical dynamic correction output vdycor i vdycor current sunk from vdycor output -1.5 -0.1 ma v vd-dc dc component of the drive signal on vdycor output r l(vdycor) =10k w 4 v i v vd-v i amplitude of v-parabola on vdy- cor output (21) vsize at medium vdc-amp (sad15h): xxxxxx00 xxxxxx01 xxxxxx10 xxxxxx11 vdc-amp at maximum vsize (sad07): x0000000b x1111111b 0.25 0.50 0.75 1.00 0.6 1.6 v v v v v v tracking of v-parabola on vdycor output with vertical position (31) vdc-amp at maximum vpos (sad08): x0000000b x1111111b 0.52 1.92 v vd v C t vr 0 = [] v vd v C t vr t vr = [] --------------------------------------------------
TDA9115 15/45 6.8 dc/dc controller section v cc = 12v, t amb = 25c note 32: a current sink is provided by the bcomp output while bout is disabled: note 33: internal reference related to v refo . the same values to be found on pin bregin, while regulation loop is stabilized. note 34: only applies to configuration specified in "test conditions" column, i.e. synchronization of bout off-to-on edge with horizontal flyback signal. refer to chapter "dc/dc controller" for more details. symbol parameter test conditions value units min. typ. max. r b+fb ext. resistance applied between bcomp output and bregin input 5k w a olg open loop gain of error amplifier on bregin input low frequency (18) 100 db f ugbw unity gain bandwidth of error am- plifier on bregin input (18) 6mhz i ri bias current delivered by regula- tion input bregin -0.2 m a i bcomp output current capability of bcomp output. hbouten = "enable" hbouten = "disable" (32) -0.5 0.5 2.0 ma ma a bisense voltage gain on bisense input 3 v thrbiscurr threshold voltage on bisense input corresponding to current limitation 1.98 2.1 2.22 v i bisense input current sourced by bisense input -1 m a i bout output current capability of bout output 010ma v bosat saturation voltage of the internal output transistor on bout i bout =10ma 0.25 0.35 v v breg regulation reference for bregin voltage (33) v refo =8v 4.7 4.8 5.0 v t btrigdel /t h delay of bout off-to-on edge after middle of flyback pulse, as part of t h (34) boutph = "0" 16 %
TDA9115 16/45 6.9 miscellaneous v cc = 12v, t amb = 25c note 35: current sunk by the pin if the external voltage is higher than one the circuit tries to force. note 36: the threshold is equal to actual v refo . note 37: in the regions of v cc where the device's operation is disabled, the h-drive, v-drive and b+-drive signals on hout, vout and bout pins, resp., are inhibited, the i 2 c bus does not accept any data. symbol parameter test conditions value units min. typ. max. vertical blanking and horizontal lock indication composite output hlckvbk i sinklckbk sink current to hlckvbk pin (35) 100 m a v olckbk output voltage on hlckvbk output 0.1 1.1 5 6 v v v v horizontal moir canceller v ac-hmoir h-moir pulse amplitude on hmoir pin rext=10k w hmoire (sad02): x0000000b x1111111b 0.1 2.1 v v v dc-hmoir dc level on hmoir pin rext=10k w 0.1 v vertical moir canceller v v-moir amplitude of modulation of v-drive sig- nal on vout pin by vertical moir. vmoire (sad0bh): x0000000b x1111111b 0 3 mv mv protection functions v thrxray input threshold on xray input (36) 7.65 7.9 8.2 v t xraydelay delay time between xray detection event and protection action 2t h v ccen v cc value for start of operation at v cc ramp-up (37) 8.5 v v ccdis v cc value for stop of operation at v cc ramp-down (37) 6.5 v control voltages on hposf pin for soft start/stop operation (18) v hon threshold for start/stop of h-drive sig- nal 1 v v bon threshold for start/stop of b-drive sig- nal 1.7 v v hbnorm f threshold for full operational duty cycle of h-drive and b-drive signals 2.4 v hpos voltage on hposf pin as function of ad- justment of hpos register normal operation hpos (sad01) 00000000b 11111111b 3.85 2.60 4.0 2.8 4.15 3.05 v v v.blank h.lock no yes yes yes no no yes no
TDA9115 17/45 7 - typical output waveforms note ( 38 ) function sad pin byte waveform effect on screen vertical size 07 vout x0000000 x1111111 vertical position 08 vout x0000000 x1000000 x1111111 s-correction 09 vout x0000000: null x1111111: max. c-correction 0a vout x0000000 x1000000 : null x1111111 v mid(vout) v amp(min) v mid(vout) v amp(max) v mid(vout) 3.5v v mid(vout) 3.5v v mid(vout) 3.5v v voamp v vos-cor v voamp t vr 0 ? t vr ? t vr t vr v voc-cor v voamp t vr 0 ? t vr t vr v voamp v voc-cor v voamp t vr 0 ? t vr t vr
TDA9115 18/45 vertical moir amplitude 0b vout x0000000: null x1111111: max. horizontal size 10h ewout 00000000 11111111 keystone correction 0d ewout x0000000 x1111111 pin cushion correction 0c ewout x0000000 x1111111 parallelogram correction 12h x0000000 x1111111 pin cushion asymmetry correction 11h x0000000 x1111111 function sad pin byte waveform effect on screen v amp t nt v (n+1)t v (n-1)t v v v-moir v amp t nt v (n+1)t v (n-1)t v t vr 0 ? t vr t vr v ew-dc(min) t vr 0 ? t vr t vr v ew-dc(max) v ew-key v ew-dc v ew-key v ew-dc t vr 0 ? t vr t vr v ew-pcc(min) t vr 0 ? t vr t vr v ew-pcc(max) internal t paralc(min) static phase t vr 0 ? t vr t vr t paralc(max) static phase t vr 0 ? t vr t vr internal t vr 0 ? t vr t vr t pcac (max) static h-phase t vr 0 ? t vr t vr t pcac (max) static h-phase
TDA9115 19/45 note 38: for any h and v correction component of the waveforms on ewout and vout pins and for internal waveform for corrections of h asymmetry, displayed in the table, weight of the other relevant components is nullified (minimum for parabola, s-correction, medium for keystone, all corner corrections, c-correction, parallelogram, parabola asymmetry correction, written in corresponding registers). vertical dynamic correction amplitude 15h vdycor xxxxxx11 application dependent xxxxxx00 function sad pin byte waveform effect on screen t vr 0 ? t vr t vr v vd-v (max) v vd-dc vd y c or po t vr 0 ? t vr t vr v vd-v (max) v vd-dc
TDA9115 20/45 8 - i 2 c bus control register map the device slave address is 8c in write mode and 8d in read mode. bold weight denotes default value at power-on-reset. i 2 c bus data in the adjustment register is buffered and internally applied with discharge of the vertical os- cillator . in order to ensure compatibility with future devices, all reserved bits should be set to 0. sadd7 d6d5d4d3d2d1d0 write mode (slave address = 8c) 00 reserved 01 hpos (horizontal position) reserved 1 000000 02 hmoir 1: separated 0 : combined hmoire (horizontal moir amplitude) 0000000 03 reserved 04 reserved 05 reserved 06 boutpol 0 : type n reserved 07 boutph 0 : h-flyback 1: h-drive vsize (vertical size) 1000000 08 ewtrhfr 0 : no tracking vpos (vertical position) 1000000 09 reserved scor (s-correction) 1000000 0a reserved ccor (c-correction) 1000000 0b reserved vmoire (vertical moir amplitude) 0000000 0c reserved pcc (pin cushion correction) 1000000 0d reserved keyst (keystone correction) 1000000 0e reserved 0f reserved 10 hsize (horizontal size) reserved 1 000000 11 reserved pcac (pin cushion asymmetry correction) 1000000 12 reserved paral (parallelogram correction) 1000000 13 reserved 14 reserved 15 reserved vdc-amp 00
TDA9115 21/45 note 39: the tv, th, tvm and thm bits are for testing purposes and must be kept at 0 by application. description of i 2 c bus switches write-to bits sad02/d7 - hmoir h orizontal moir characteristics 0: adapted to an architecture with eht gener- ated in deflection section 1: adapted to an architecture with separated deflection and eht sections sad06/d7 - boutpol pol arity of b+ drive signal on bout pin 0: adapted to n type of power mos - high level to make it conductive 1: adapted to p type of power mos - low level to make it conductive sad07/d7 - boutph ph ase of start of b+ drive signal on bout pin 0: just after horizontal flyback pulse 1: with one of edges of line drive signal on hout pin, selected by bohedge bit sad08/d7 - ewtrhfr tr acking of all corrections contained in wave- form on pin ewout with h orizontal fr equency 0: not active 1: active sad16/d0 - hlocken enable of output of h orizontal pll1 lock /unlock status signal on pin hlckvbk 0: disabled, vertical blanking only on the pin hlckvbk 1: enabled sad16/d1 - pll1inhen en able of inh ibition of horizontal pll1 during extracted vertical synchronization pulse 0: disabled, pll1 is never inhibited 1: enabled sad16/d2 - pll1pump horizontal pll1 charge pump current 0: slow pll1, low current 1: fast pll1, high current sad16/d5 - vsyncsel v ertical sync hronization input sel ection be- tween the one extracted from composite hv sig- nal on pin h/hvsyn and the one on pin vsyn. no effect if vsyncauto bit is at 1. 0: v. sync extracted from composite signal on h/hvsyn pin selected 1: v. sync applied on vsyn pin selected sad16/d6 - vsyncauto v ertical sync hronization input selection auto- matic mode. if enabled, the device automatically selects between the vertical sync extracted from composite hv signal on pin h/hvsyn and the one on pin vsyn, based on detection mecha- nism. if both are present, the one coming first is kept. 0: disabled, selection done according to bit vsyncsel 1: enabled, the bit vsyncsel has no effect sad16/d7 - xrayreset reset to 0 of xray effected with ack bit of i 2 c bus data transfer into register containing the xrayreset bit. 0: no effect 1: reset with automatic return of the bit to 0 this bit is not latched, it will return to 0 by itself. sad17/d0 - blankmode blank ing operation mode 0: blanking pulse starting with detection of vertical synchronization pulse and ending with end of vertical oscillator discharge 16 xrayreset 0 : no effect 1: reset vsyncauto 1 : on vsyncsel 0:comp 1 :sep 00 pll1pump 1: fast 0 : slow pll1inhen 1 : on hlocken 1 : on 17 tv 0 : off ( 39 ) th 0 : off ( 39 ) tvm 0 : off ( 39 ) thm 0 : off ( 39 ) bohedge 0 : falling hbouten 0 : disable vouten 0 : disable blankmode 1 : perm. sadd7 d6d5d4d3d2d1d0
TDA9115 22/45 (start of vertical sawtooth ramp on the vout pin) 1: permanent blanking - high blanking level in composite signal on pin hlckvbk is per- manent sad17/d1 - vouten v ertical out put en able 0: disabled, v offvout on vout pin (see 6.5 vertical section) 1: enabled, vertical ramp with vertical position offset on vout pin sad17/d2 - hbouten h orizontal and b + out put en able 0: disabled, levels corresponding to power transistor off on hout and bout pins (high for hout, high or low for bout, depending on boutpol bit). 1: enabled, horizontal deflection drive signal on hout pin providing that it is not inhibited by another internal event (activated xray protection). b+ drive signal on bout pin. programming the bit to 1 after prior value of 0, will initiate soft start mechanism of horizontal drive and of b+ dc/dc convertor sad17/d3 - bohedge selection of edge of h orizontal drive signal to phase b + drive o utput signal on bout pin. only applies if the bit boutph is set to 1, otherwise bohedge has no effect. 0: falling edge 1: rising edge sad17/d4,d5,d6,d7 - thm, tvm, th, tv test bits. they must be kept at 0 level by appli- cation s/w.
TDA9115 23/45 9 - operating description 9.1 supply and control 9.1.1 power supply and voltage references the device is designed for a typical value of power supply voltage of 12 v. in order to avoid erratic operation of the circuit at power supply ramp-up or ramp-down, the value of v cc is monitored. see figure 1 and electrical specifications. at switch-on, the device enters a normal operation as the supply voltage exceeds v ccen and stays there until it decreases below v ccdis . the two thresholds provide, by their differ- ence, a hysteresis to bridge potential noise. out- side the normal operation, the signals on hout, bout and vout outputs are inhibited and the i 2 c bus interface is inactive (high impedance on sda, scl pins, no ack), all i 2 c bus control registers being reset to their default values (see chapter i 2 c bus control register map on page 20). figure 1. supply voltage monitoring internal thresholds in all parts of the circuit are de- rived from a common internal reference supply v refo that is lead out to refout pin for external fil- tering against ground as well as for external use with load currents limited to i refo . the filtering is necessary to minimize interference in output sig- nals, causing adverse effects like e.g. jitter. 9.1.2 i 2 c bus control the i 2 c bus is a 2 line bi-directional serial commu- nication bus introduced by philips. for its general description, refer to corresponding philips i 2 c bus specification. this device is an i 2 c bus slave, compatible with fast (400khz) i 2 c bus protocol, with write mode slave address of 8c. integrators are employed at the scl (serial clock) input and at the input buffer of the sda (serial data) input/output to filter off the spikes of up to 50ns. the device supports multiple data byte messages (with automatic incrementation of the i 2 c bus sub- address) as well as repeated start condition for i 2 c bus subaddress change inside the i 2 c bus messages. all i 2 c bus registers with specified i 2 c bus subaddress are of write only type. for the i 2 c bus control register map, refer to chap- ter i 2 c bus control register map on page 20. 9.2 sync. processor 9.2.1 synchronization signals the device has two inputs for ttl-level synchroni- zation signals, both with hysteresis to avoid erratic detection and with a pull-down resistor. on h/ hvsyn input, pure horizontal or composite hori- zontal/vertical signal is accepted. on vsyn input, only pure vertical sync. signal is accepted. both positive and negative polarities may be applied on either input, see figure 2. polarity detector and programmable inverter are provided on each of the two inputs. the signal applied on h/hvsyn pin, after polarity treatment, is directly lead to horizon- tal part and to an extractor of vertical sync. pulses, working on principle of integration, see figure 3. the vertical sync. signal applied to the vertical de- flection processor is selected between the signal extracted from the composite signal on h/hvsyn input and the one applied on vsyn input. the se- lector is controlled by vsyncsel i 2 c bus bit. besides the polarity detection, the device is capa- ble of detecting the presence of sync. signals on each of the inputs and at the output of vertical sync. extractor. the device is equipped with an au- tomatic mode (switched on or off by vsyncauto i 2 c bus bit) that uses the detection information. normal operation hysteresis v ccen v ccdis t disabled disabled v (vcc) v cc
TDA9115 24/45 figure 2. horizontal sync signal figure 3. extraction of v-sync signal from h/v-sync signal 9.2.2 automatic sync. selection mode i 2 c bus bit vsyncauto is set to 1. in this mode, the device itself controls the i 2 c bus bits switching the polarity inverters and the vertical sync. signal se- lector (vsyncsel), using the information provided by detection circuitry. if both extracted and pure vertical sync. signals are present, the one already selected is maintained. no intervention of the mcu is necessary. 9.3 horizontal section 9.3.1 general the horizontal section consists of two plls with various adjustments and corrections, working on horizontal deflection frequency, then phase shift- ing and output driving circuitry providing h-drive signal on hout pin. input signal to the horizontal section is output of the polarity inverter on h/ hvsyn input. the device ensures automatically that this polarity be always positive. 9.3.2 pll1 the pll1 block diagram is in figure 5. it consists of a voltage controlled oscillator (vco), a shaper with adjustable threshold, a charge pump with inhi- bition circuit, a frequency and phase comparator and timing circuitry. the goal of the pll1 is to make the vco ramp signal match in frequency the sync. signal and to lock this ramp in phase to the sync. signal, with a possibility to adjust a perma- nent phase offset. on the screen, this offset re- sults in the change of horizontal position of the pic- ture. the loop, by tuning the vco accordingly, gets and maintains in coincidence the rising edge of input sync. signal with signal ref1, which is de- rived from the vco ramp by a comparator with threshold adjustable through hpos i 2 c bus con- trol. the coincidence is identified and flagged by lock detection circuit on pin hlckvbk . the charge pump provides positive and negative currents charging the external loop filter on hposf pin. the loop is independent of the trailing edge of sync. signal and only locks to its leading edge. by design, the pll1 does not suffer from any dead band even while locked. the speed of the pll1 depends on the current value provided by the charge pump. while not locked, the current is very low, to slow down the changes of vco frequency and thus protect the external power components at sync. signal change. in locked state, the cur- rents are much higher, two different values being selectable via pll1pump i 2 c bus bit to provide a mean to control the pll1 speed by s/w. lower values make the pll1 slower, but more stable. higher values make it faster and less stable. in general, the pll1 speed should be higher for high deflection frequencies. the response speed and stability (jitter level) depends on the choice of ex- ternal components making up the loop filter. a crc filter is generally used (see figure 4 on page 25). positive negative t h t pulsehsyn h/v-sync integration extracted t extrv t h t pulsehsyn v-sync internal
TDA9115 25/45 figure 4. h-pll1 filter configuration the pll1 is internally inhibited during extracted vertical sync. pulse (if any) to avoid taking into ac- count missing or wrong pulses on the phase com- parator. inhibition is obtained by forcing the charge pump output to high impedance state. the inhibi- tion mechanism can be disabled through pll1pump i 2 c bus bit. the figure 7, in its upper part, shows the position of the vco ramp signal in relation to input sync. pulse for three different positions of adjustment of horizontal position control hpos . figure 5. horizontal pll1 block diagram figure 6. horizontal oscillator (vco) schematic diagram hpll1f 9 r 2 c 1 c 2 4 lock status pll inhibition hposf shaper low high lock comp charge pump hpll1f r0 c0 86 vco hosc (i 2 c) hpos input interface h/hvsyn sync 9 10 pll1pump v-sync (extracted) pll1inhen (i 2 c) hoscf detector 1 polarity v-sync extracted ref1 (pin & i 2 c) (i 2 c) pll1 rs flip-flop co v hothrhi 4 i 0 i 0 2 hpll1f i 0 ro 9 + - (pll1 filter) 6 hoscf + - + - 4 v hothrlo v hothrlo v hothrhi 8 from charge pump v ho vco discharge control
TDA9115 26/45 9.3.3 voltage controlled oscillator the vco makes part of both pll1 and pll2 loops, being an output to pll1 and input to pll2. it delivers a linear sawtooth. figure 6 ex- plains its principle of operation. the linears are ob- tained by charging and discharging an external ca- pacitor on pin co, with currents proportional to the current forced through an external resistor on pin ro, which itself depends on the input tuning volt- age v ho (filtered charge pump output). the rising and falling linears are limited by v hothrlo and v hothrhi thresholds filtered through hoscf pin. at no signal condition, the v ho tuning voltage is clamped to its minimum (see chapter electri- cal parameters and operating condi- tions, part horizontal section), which corre- sponds to the free-running vco frequency f ho(0) . refer to note1 for the formula to calculate this fre- quency using external components values. the ra- tio between the frequency corresponding to maxi- mum v ho and the one corresponding to minimum v ho (free-running frequency) is about 4.5. this range can easily be increased in the application. the pll1 can only lock to input frequencies falling inside these two limits. 9.3.4 pll2 the goal of the pll2 is, by means of phasing the signal driving the power deflection transistor, to lock the middle of the horizontal flyback to a cer- tain threshold of the vco sawtooth. this internal threshold is affected by geometry phase correc- tions, like e.g., parallelogram. the pll2 is much faster than pll1 to be able to follow the dynamism of this phase modulation. the pll2 control current (see figure 7) is significantly increased during dis- charge of vertical oscillator (during vertical retrace period) to be able to make up for the difference of dynamic phase at the bottom and at the top of the picture. the pll2 control current is integrated on the external filter on pin hpll2c to obtain smoothed voltage, used, in comparison with vco ramp, as a threshold for h-drive rising edge gener- ation. as both leading and trailing edges of the h-drive signal in the figure 7 must fall inside the rising part of the vco ramp, an optimum middle position of the threshold has been found to provide enough margin for horizontal output transistor storage time as well as for the trailing edge of h-drive signal with maximum duty cycle. yet, the constraints thereof must be taken into account while consider- ing the application frequency range and h-flyback duration. the figure 7 also shows regions for ris- ing and falling edges of the h-drive signal on hout pin. as it is forced high during the h-flyback pulse and low during the vco discharge period, no edge during these two events takes effect. the flyback input configuration is in figure 8. 9.3.5 dynamic pll2 phase control the dynamic phase control of pll2 is used to compensate for picture asymmetry versus vertical axis across the middle of the picture. it is done by modulating the phase of the horizontal deflection with respect to the incoming video (synchroniza- tion). inside the device, the threshold v s(0) is com- pared with the vco ramp, the pll2 locking the middle of h-flyback to the moment of their match. the dynamic phase is obtained by modulation of the threshold by correction waveforms. refer to figure 12 and to chapter typical output waveforms. the correction waveforms have no effect in vertical middle of the screen (for mid- dle vertical position). as they are summed, their ef- fect on the phase tends to reach maximum span at top and bottom of the picture. as all the compo- nents of the resulting correction waveform (linear for parallelogram correction and parabola of 2nd order for pin cushion asymmetry correction) are generated from the output vertical deflection drive waveform, they both track with real vertical ampli- tude and position (including breathing compensa- tion), thus being fixed on the screen. refer to i 2 c bus control register map on page 20 for details on i 2 c bus controls.
TDA9115 27/45 figure 7. horizontal timing diagram figure 8. hfly input configuration 9.3.6 output section the h-drive signal is inhibited (high level) during flyback pulse, and also when v cc is too low, when i 2 c bus bit hbouten is set to 0 (default position). the pll2 is followed by a rapid phase shifting which accepts the signal from h-moir canceller (see sub chapter horizontal moir cancellation on page 27) the output stage consists of a npn bipolar tran- sistor, the collector of which is routed to hout pin (see figure 9). figure 9. hout configuration non-conductive state of hot (horizontal output transistor) must correspond to non-conductive state of the device output transistor. 9.3.7 soft-start and soft-stop on h-drive the soft-start and soft-stop procedure is carried out at each switch-on or switch-off of the h-drive signal via hbouten i 2 c bus bit to protect external power components. by its second function, the ex- ternal capacitor on pin hposf is used to time out this procedure, during which the duty cycle of h- drive signal starts at its maximum (t hoff /t h for soft start/stop in electrical specifications) and slowly decreases. this is controlled by voltage on pin hposf. see figure 10 and sub chapter safety functions on page 33. 9.3.8 horizontal moir cancellation the horizontal moir canceller is intended to blur a potential beat between the horizontal video pixel period and the crt pixel width, which causes vis- ible moir patterns in the picture. on pin hmoir, it generates a square line-synchro- nized waveform with amplitude adjustable through hmoire i 2 c bus control. the behaviour of horizontal moir is to be opti- mised for different deflection design configurations using hmoir i 2 c bus bit. this bit is to be kept at 0 for common architecture (b+ and eht common regulation) and at 1 for separated architecture (b+ and eht each regulated separately). h-flyback pll2 h-drive current v thrhfly control + - (on hout) t s t hoff h-drive region h-drive region t ph(max) inhibited t s : hot storage time h-osc v s(0) 7/8t h t h v hothrhi max. med. min. v hposf h-sync (polarized) ref1 t hph min max hpos (i 2 c) max. med. min. pll1 lock (internal) v hothrlo (vco) pll2 pll1 control on forced high forced low off on gnd ~20k w hfly 12 ~500 w int. ext. 26 int. ext. hout
TDA9115 28/45 figure 10. control of hout and bout at start/stop at nominal v cc 9.4 vertical section 9.4.1 general the goal of the vertical section is to drive vertical deflection output stage. it delivers a sawtooth waveform with an amplitude independent of de- flection frequency, on which vertical geometry cor- rections of c- and s-type are superimposed (see chapter typical output waveforms). block diagram is in figure 11. the sawtooth is ob- tained by charging an external capacitor on pin vcap with controlled current and by discharging it via transistor q1. this is controlled by the con- troller. the charging starts when the voltage across the capacitor drops below v vob threshold. the discharging starts either when it exceeds v vot threshold or a short time after arrival of synchroni- zation pulse. this time is necessary for the agc loop to sample the voltage at the top of the saw- tooth. the v vob reference is routed out onto vo- scf pin in order to allow for further filtration. the charging current influences amplitude and shape of the sawtooth. just before the discharge, the voltage across the capacitor on pin vcap is sampled and stored on a storage capacitor con- nected on pin vagccap. during the following ver- tical period, this voltage is compared to internal reference ref (v vot ), the result thereof control- ling the gain of the transconductance amplifier pro- viding the charging current. speed of this agc loop depends on the storage capacitance on pin vagccap. on the screen, this corresponds to sta- bilized vertical size of picture. after a change of frequency on the sync. input, the stabilization time depends on the frequency difference and on the capacitor value. the lower its value, the shorter the stabilization time, but on the other hand, the lower the loop stability. a practical compromise is a capacitance of 470nf. the leakage current of this capacitor results in difference in amplitude be- tween low and high frequencies. the higher its parallel resistance r l(vagccap) , the lower this dif- ference. when the synchronization pulse is not present, the charging current is fixed. as a consequence, the free-running frequency f vo(0) only depends on the value of the capacitor on pin vcap. it can be roughly calculated using the following formula f vo(0) = the frequency range in which the agc loop can regulate the amplitude also depends on this ca- pacitor. the c- and s-corrections of shape serve to com- pensate for the vertical deflection system non-line- arity. they are controlled via ccor and scor i 2 c bus controls. shape-corrected sawtooth with regulated ampli- tude is lead to amplitude control stage. the dis- t v (hposf) soft start soft stop normal operation start hout start bout stop hout stop bout hout h-duty cycle bout (positive) b-duty cycle 100% 0% v hon v bon v hbnorm v hposmax v hposmin hpos (i 2 c) range minimum value maximum value c (vcap) . 100hz 150nf
TDA9115 29/45 charge exponential is replaced by v vob level, which, under control of the controller, cre- ates a rapid falling edge and a flat part before be- ginning of new ramp. mean value of the waveform output on pin vout is adjusted by means of vpos i 2 c bus control, its amplitude through vsize i 2 c bus control. vertical moir is superimposed. the biasing voltage for external dc-coupled verti- cal power amplifier is to be derived from v refo voltage provided on pin refout, using a resistor di- vider, this to ensure the same temperature drift of mean (dc) levels on both differential inputs and to compensate for spread of v refo value (and so mean output value) between particular devices. 9.4.2 vertical moir to blur the interaction of deflection lines with crt mask grid pitch that can generate moir pattern, the picture position is to be alternated at frame fre- quency. for this purpose, a square waveform at half-frame frequency is superimposed on the out- put waveforms dc value. its amplitude is adjusta- ble through vmoire i 2 c bus control,. figure 11. vertical section block diagram 9.5 ew drive section the goal of the ew drive section is to provide, on pin ewout, a waveform which, used by an exter- nal dc-coupled power stage, serves to compen- sate for those geometry errors of the picture that are symmetric versus vertical axis across the mid- dle of the picture. the waveform consists of an adjustable dc value, corresponding to horizontal size, a parabola of 2nd order for pin cushion correction and a linear for keystone correction. all of them are adjustable via i 2 c bus, see i 2 c bus control register map on page 20. refer to figure 12, figure 13 and to chapter typ- ical output waveforms. the correction waveforms have no effect in the vertical middle of the screen (if the vpos control is adjusted to its medium value). as they are summed, the resulting waveform tends to reach its maximum span at top and bottom of the picture. the voltage at the ewout is top and bottom limited (see parameter v ew ). according to figure 13, especially the bot- tom limitation seems to be critical for maximum horizontal size (minimum dc). actually it is not critical since the parabola component must always be applied. as all the components of the resulting correction waveform are generated from the out- 2 synchro polarity controller discharge 22 sampling sampling capacitance s-correction ccor c-correction 18 23 v vob sawtooth ref charge current transconductance amplifier (i 2 c) scor (i 2 c) 20 vagccap discharge ccor vsize (i 2 c) vmoire (i 2 c) vpos (i 2 c) 19 voscf vout vehtin vcap vsyn osc cap. q1
TDA9115 30/45 put vertical deflection drive waveform, they all track with real vertical amplitude and position (in- cluding breathing compensation), thus being fixed vertically on the screen. they are also affected by c- and s-corrections. the sum of components oth- er than dc is affected by value in hsize i 2 c bus control in reversed sense. refer to electrical spec- ifications for value. the dc value, adjusted via hsize control, is also affected by voltage on heh- tin input, thus providing a horizontal breathing compensation (see electrical specifications for val- ue). the resulting waveform is conditionally multi- plied with voltage on hpll1f, which depends on frequency. refer to electrical specifications for val- ue and more precision. this tracking with frequen- cy provides a rough compensation of variation of picture geometry with frequency and allows to fix the adjustment ranges of i 2 c bus controls through- out the operating range of horizontal frequencies. it can be switched off by ewtrhfr i 2 c bus bit (off by default). the ew waveform signal is buffered by an npn emitter follower, the emitter of which is directly routed to ewout output, with no internal resistor to ground. it is to be biased externally. figure 12. geometric corrections schematic diagram vertical ramp v mid(vout) 2 to horizontal dyn. phase control ewout keyst pcc vdc-amp vdycor tracking with hor frequency tracking hehtin/hsize hehtin hsize 17 32 24 23 controls: one-quadrant two-quadrant (i 2 c) (i 2 c) (i 2 c) pcac (i 2 c) vout paral (i 2 c)
TDA9115 31/45 figure 13. ewout output waveforms 9.6 dynamic correction output section 9.6.1 vertical dynamic correction output vdycor a parabola at vertical deflection frequency is avail- able on pin vdycor. its amplitude is adjustable via vdc-amp i 2 c bus control. it tracks with real verti- cal amplitude and position (including breathing compensation). it is also affected by c- and s-cor- rections. the use of this correction waveform is up to the application (e.g. dynamic focus). 9.7 dc/dc controller section the section is designed to control a switch-mode dc/dc converter. a switch-mode dc/dc conver- tor generates a dc voltage from a dc voltage of different value (higher or lower) with little power losses. the dc/dc controller is synchronized to horizontal deflection frequency to minimize poten- tial interference into the picture. its operation is similar to that of standard uc3842. the schematic diagram of the dc/dc controller is in figure 14. the bout output controls an external switching circuit (a mos transistor) delivering pulses synchronized on horizontal deflection fre- quency, the phase of which depends on i 2 c bus configuration, see the table at the end of this chap- ter. their duration depends on feedback provided to the circuit, generally a copy of dc/dc converter output voltage and a copy of current passing through the dc/dc converter circuitry (e.g. current through external power component). the polarity of the output can be controlled by boutpol i 2 c bus bit. a npn transistor open-collector is routed out to the bout pin. during the operation, a sawtooth is to be found on pin bisense, generated externally by the applica- tion. according to boutph i 2 c bus bit, the r-s flip- flop is set either at h-drive signal edge (rising or falling, depending on bohedge i 2 c bus bit), or a keystone pcc alone alone v (vcap) 0 t vr t vr 0 v (ewout) operating range v ew-pcc v ew-key v ew v ew-dc v (heht) v refo v heht (min) hsize (i 2 c) m i n i m u m m ed i u m m a x i m u m v ew (min) v ew (max) non-authorized region vertical sawtooth t vr v (vcap) 0 t vr t vr 0 v refo v heht (min) breathing compensation
TDA9115 32/45 certain delay (t btrigdel /t h ) after middle of h-fly- back. the output is set on at the end of a short pulse generated by the monostable trigger. timing of reset of the r-s flip-flop affects duty cy- cle of the output square signal and so the energy transferred from dc/dc converter input to its out- put. a reset edge is provided by comparator c2 if the voltage on pin bisense exceeds the internal threshold v thrbiscurr . this represents current limi- tation if a voltage proportional to the current through the power component or deflection stage is available on pin bisense. this threshold is af- fected by the voltage on pin hposf, which rises at soft start and descends at soft stop. this ensures self-contained soft control of duty cycle of the out- put signal on pin bout. refer to figure 10. another condition for the reset of the r-s flip-flop, or-ed with the one described before, is that the voltage on pin bisense exceeds the voltage v c1 , which depends on the voltage applied on input bisense of the error amplifier o1. the two voltages are compared, and the reset signal generated by the comparator c1. the error amplifier amplifies (with a factor defined by external components) the dif- ference between the input voltage proportional to dc/dc convertor output voltage and internal refer- ence v breg . both step-up (dc/dc converter output voltage higher than its input voltage) and step-down (out- put voltage lower than input) are possible. dc/dc controller off-to-on edge timing figure 14. dc/dc converter controller block diagram boutph (sad07/ d7) bohedge (sad17/ d3) timing of off-to-on transition on bout output 0 dont care middle of h-flyback plus t btrigdel 1 0 falling edge of h-drive signal 1 1 rising edge of h-drive signal c1 bregin bcomp bisense bout n type soft start h-drive edge h-flyback + - + - + - s q r ~500ns monostable hbouten p type v cc feedback c2 boutpol (i 2 c) xrayalarm (i 2 c) boutph (i 2 c) hposf v thrbiscurr (+delay) bohedge (i 2 c) 2r r v breg i1 i2 i3 v c1 o1
TDA9115 33/45 9.8 miscellaneous 9.8.1 safety functions the safety functions comprise supply voltage monitoring with appropriate actions, soft start and soft stop features on h-drive and b-drive signals on hout and bout outputs and x-ray protection. for supply voltage supervision, refer to paragraph power supply and voltage references on page 23 and figure 1. a schematic diagram putting togeth- er all safety functions and composite pll1 lock and v-blanking indication is in figure 15. 9.8.2 soft start and soft stop functions for soft start and soft stop features for h-drive and b-drive signal, refer to paragraph soft-start and soft-stop on h-drive on page 27 and sub chapter- dc/dc controller section on page 31, re- spectively. see also the figure 10. regardless why the h-drive or b-drive signal are switched on or off (i 2 c bus command, power up or down, x-ray protection), the signals always phase-in and phase-out in the way drawn in the figure, the first to phase-in and last to phase-out being the h-drive signal, which is to better protect the power stages at abrupt changes like switch-on and off. the tim- ing of phase-in and phase-out only depends on the capacitance connected to hposf pin which is virtually unlimited for this function. yet it has a dual function (see paragraph pll1 on page 24), so a compromise thereof is to be found. 9.8.3 x-ray protection the x-ray protection is activated if the voltage lev- el on xray input exceeds v thrxray threshold. as a consequence, the h-drive and b-drive signals on hout and bout outputs are inhibited (switched off) after a 2-horizontal deflection line delay provided to avoid erratic excessive x-ray condition detec- tion at short parasitic spikes. this protection is latched; it may be reset either by v cc drop or by i 2 c bus bit xrayreset (see chap- ter i 2 c bus control register map on page 20).
TDA9115 34/45 figure 15. safety functions - block diagram v cc supervision vcc hbouten xrayreset r h-drive inhibition v-drive inhibition b-drive inhibition hlckvbk soft start & stop h-drive inhibit hposf vouten r s h-lock detector hlocken blankmode v-sync r s q + s _ + _ v-sawtooth discharge 12 hfly 29 i 2 c i 2 c i 2 c i 2 c i 2 c 10 (timing) 3 i 2 c 3 i 2 c bit pin int. signal v ccen v ccdis v thrhfly + _ 25 xray v thrxray h-vco l2=h-lock/unlock level l1=no blank/blank level l3=l1+l2 in out :2 q (overrule) b-drive inhibit discharge control
TDA9115 35/45 9.8.4 composite output hlckvbk the composite output hlckvbk provides, at the same time, information about lock state of pll1 and early vertical blanking pulse. as both signals have two logical levels, a four level signal is used to define the combination of the two. schematic di- agram putting together all safety functions and composite pll1 lock and v-blanking indication is in figure 15, the combinations, their respective levels and the hlckvbk configuration in figure 16. the early vertical blanking pulse is obtained by a logic combination of vertical synchronization pulse and pulse corresponding to vertical oscillator dis- charge. the combination corresponds to the draw- ing in figure 16. the blanking pulse is started with the leading edge of any of the two signals, which- ever comes first. the blanking pulse is ended with the trailing edge of vertical oscillator discharge pulse. the device has no information about the vertical retrace time. therefore, it does not cover, by the blanking pulse, the whole vertical retrace period. by means of blankmode i 2 c bus bit, when at 1 (default), the blanking level (one of two ac- cording to pll1 status) is made available on the hlckvbk permanently. the permanent blanking, irrespective of the blankmode i 2 c bus bit, is also provided if the supply voltage is low (under v ccen or v ccdis thresholds), if the x-ray protection is ac- tive or if the v-drive signal is disabled by vouten i 2 c bus bit. figure 16. levels on hlckvbk composite output hlckvbk 3 v cc hpll1 locked v-early blanking yes yes no yes no no yes no i sinklckblk v olckblk l1 (h) +l2 (l) l1 (l) +l2 (h) l1 (h) +l2 (h) l1 (l) +l2 (l) l1 - no blank/blank level l2 - h-lock/unlock level
TDA9115 36/45 figure 17. ground layout recommendations TDA9115 general ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TDA9115 37/45 10 - internal schematics figure 18. figure 19. figure 20. figure 21. figure 22. figure 23. pins 1-2 h/hvsyn vsyn 5v 200 w hlckvbk l 3 12v refout 13 12v hoscf pin 4 pin 13 hpll2c 5 12v 13 refout 12v refout 13 6 c0 r0 8 12v refout 13
TDA9115 38/45 figure 24. figure 25. figure 26. figure 27. figure 28. figure 29. hpll1f 9 refout 12v hposf 10 hmoir 11 12v 5v 5v 12v hfly 12 14 bcomp bregin 12v 15
TDA9115 39/45 figure 30. figure 31. figure 32. figure 33. figure 34. figure 35. bisense 16 12v 12v 18 vehtin hehtin 17 12v voscf pin 13 19 vagccap 12v 20 vcap 22 12v vout 23 12v
TDA9115 40/45 figure 36. figure 37. figure 38. figure 39. 24 ewout 12v 32 vdycor 12v xray 25 26 hout 28 bout 12v 30 scl 31sda
TDA9115 41/45 11 - package mechanical data 32 pins - plastic shrink dimensions millimeters inches min. typ. max. min. typ. max. a 3.556 3.759 5.080 0.140 0.148 0.200 a1 0.508 0.020 a2 3.048 3.556 4.572 0.120 0.140 0.180 b 0.356 0.457 0.584 0.014 0.018 0.023 b1 0.762 1.016 1.397 0.030 0.040 0.055 c .203 0.254 0.356 0.008 0.010 0.014 d 27.43 27.94 28.45 1.080 1.100 1.120 e 9.906 10.41 11.05 0.390 0.410 0.435 e1 7.620 8.890 9.398 0.300 0.350 0.370 e 1.778 0.070 ea 10.16 0.400 eb 12.70 0.500 l 2.540 3.048 3.810 0.100 0.120 0.150 ea eb e1 e d 32 17 16 1 stand-off e b1 b a2 a1 a l c
TDA9115 42/ 45 12 - glossary ac a lternate c urrent ack ack nowledge bit of i 2 c-bus transfer agc a utomatic g ain c ontrol comp comp arator crt c athode r ay t ube dc d irect c urrent eht e xtra h igh v oltage ew e ast- w est h/w h ard w are hot h orizontal o utput t ransistor i 2 ci nter- i ntegrated c ircuit iic i nter- i ntegrated c ircuit mcu m icro- c ontroller u nit nand n egated and (logic operation) npn n egative- p ositive- n egative osc osc illator pll p hase- l ocked l oop pnp p ositive- n egative- p ositive ref ref erence rs, r-s r eset- s et s/w s oft w are ttl t ransistor t ransistor l ogic vco v oltage- c ontrolled o scillator
revision follow-up product preview june 2000 version 2.0 document created (issued from tda9112) work on figures and text; version finalized and displayed on intranet. july 2000 version 2.1 sentence modified in first page : the internal sync processor.;. replaced by :the device only requires..; bloc diagram : addition of hsize under e/w correction quick reference data: addition of parrallelogram register map: subaddress 08: 0:no tracking few corrections in text. preliminary data september 2000 version 3:0 uniformity in the writing of cross references for notes. in internal schematics, correction of figure for pin 11. in bloc diagram: the line between pll2 and hmoir controller has been deleted in horizontal moir cancellation: 1 sentence changed vdc amp replaced by vdc-amp in electrical parameters: d v hmoir becomes d v ac-hmoir addition of v dc-hmoir ,. january 11, 2001 version 3.1 page 6: value for autosync frequency ratio replaced : 4.28 instead of 4.5 previously. april 19, 2001 version 3.2 page 16 section 6.9 .vtrh-xray: new values 7.65 min, 7.9 typ., 8.2 max. datasheet july 18, 2001 version 4.0 section 9.4.1 right column"the higher its value,..." ---> "the lower its value" section 9.5 ."...at the vertical middle..." ---> "...in the vertical middle..." section 6.6 : addition of [fmax] to parameter " d vew/vew[fmax]. d vho" .and changed its value to 20 note 28: added: vew[fmax] is the value at condition vho>vhothrfr. section 6.4 : addition of min and max values for v hposf and v tophpll2c section 6.5 addition of min and max values for v vob + correction of typ. value 2
section 6.8 addition of min and max values for v thrblscurr and v breg , max value added for v bosat section 6.9 addition of min and max values for v hpos section 9.4 stabilizing time changed to stabilization time (twice) section 6.9 : max values for vertical moir cancellers moved to typ. values october 23, 2001 version 4.1 section 9.5 correction of figure 13: ewout output waveforms september 2003 version 4.1 publication on www.st.com
TDA9115 45/45 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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